1. What are the two famous architecture of CPU ?

2. What is the difference between Harvard and Von Neuman architecture ?

3. What is the use of instruction cache ?

4. Is it good to have more instruction cache or data cache ?

5. What is the use of data cache ?

6. What is the use of TLB ?

7. What do you mean by Cache Hit or Cache Miss ? What is cache hit rate ? 

8. What is the difference between read miss and write miss ?

9. How does cache hit or cache miss determine the selection of processor ?

10. What is cache line or cache block ?

11. What is write-back or copy-back cache ?

12. What is the need for cache coherence protocol ?

13. What are the 3 kinds of cache misses ? or Which of the below causes the most delay and why ? Instruction read miss, Data read miss, and Data write miss . 

14. What is boundary alignment and what is the use of it ?

15. What will happen if the data being fetched exceeds the cache line size ? or

if the data is not being aligned at the beginning of cache block ?

16. How can grouping of data can improve the cache based operations from application-side ?

17. What is cache prefetch ?

18. Brief up on pipelined versus Run-to-Completion processor software architecture ?

19. Why multicore processors are preferred to improve performance rather than trying to make a single processor based system faster ?

20. Does memory access speed varies at various stages ? Which is the fastest memory that you can directly deal with from a processor or Which type of memory of a CPU has almost zero percent latency ?

21. What is temporal locality and spatial locality ?

22. What are the applications of temporal locality and spatial locality ? or where are they applied in a CPU architecture ?

23. What is the use of Shadow Registers in ARM architecture ?

24. How will you calculate the idle time off a processor ?

25. How will you identify the endianness of a processor programatically ?

26. What is Memory Overlay ?

27. Tell about Bank Switching ?

28. What are the Disadvantages of Bank Switching ?

29. Why is the size of L1 cache smaller than that of the L2 cache in most of the processors ?

30. When should one use polling method and when should one use interrupt based method ? Are there scenarios in which both can be used ?

31. What could be the better way to determine the exact locations in which the prefetch instruction should be used ?

32. Considering that a processor runs at 100 MHz and the data is coming to the processor from an external device/peripheral at the rate of 1000 Mbit/s (8 Bits/Clockcycle @ 125 MHz), which is the best way to handle traffic that comes at a higher speed to the processor ?

33. Consider that there are 100 plus ways of interrupts occuring from various sensors. There are chances that all can occur at the same time too. How can the software be designed to handle it efficiently ?

34. What is Write-Back Cache ?

35. What is Write-Through Cache ?

36. What is cache coherency ?

37. What is Clock Cycles Per Instruction (CPI) ?

38. What is IPC(Instructions per cycle) ?

39. Tell about the 'nested interrupt handler' , 'reentrant interrupt handler' and ' prioritized direct interrupt handler' ?

40. What is Memory Banking ? Explain w.r.t 8051 architecture 

41. What is Primary Memory and What is Secondary Memory ?

42. What is the advantage of MMU ?

43. How do you determine the direction of stack growth ?

44. What is the debugger that you have used ?

45. Have you used any emulator. If yes, how have you used it ?

46. Can you tell a scenario that was very difficult to solve / fix ?

47. Have you worked on optimization w.r.t memory usage ? What techniques have you followed to optimize ?

47. Have you worked on optimization w.r.t throughput / speed ? What techniques have you followed to optimize ?

48. What kind of co-processors have you used ?

1. Will increasing the number of cores, increase the throughput of your system ?

2. What are the general methods of communication between the cores ?

3. When is it better to use single core processor compared to multi-core processor ?

4. If the CPU in a multi-core processor updates the data in the cache, copies of data in caches associated with other cores will become stale. How is the multicore processor designed to handle this scenario ?

5. What is 'Run to Completion' software architecture ?

6. What is a 'Pipelined' software architecture ?

7. What is the difference between 'Run to Completion' and 'Pipelined' software architecture ?

8. How is the debugging and testing environment in the case of multithreaded/multiprocessing applications ?

9. At what point does adding more processors or computers to the computation pool slow things down instead of speeding them up?

10. Is there an optimal number of processors for any given parallel program?

11. How Many Processes or Threads are enough for an application ?

1. Expansion of uC/OS-II ?

2. What is the footprint size of uC/OS-II ? 

3. Roughly, how man lines of code is it ?

4. What type of scheduler is supported by uC/OS-II ?

5. Does uc/OS-II RTOS support nested interrupts ? To how many levels ?

6. What are the APIs that play a significant role in uC/OS-II initialization ?

7. Binary semaphore in uC/OS-II use priority cieling to address priority inversion - True/False ?

8. What is the exact context switch time in uC/OS-II RTOS ?

9. Does uC/OS-II RTOS support MMU ?

10. Is it possible to use uC/OS-II RTOS without MMU ?

11. What could be the best reason/scenario for selecting uC/OS-II RTOS ?

12. Which is the lowest prirority task in uC/OS-II RTOS ?

13. The idle task is always the lowest-priority task and can not be deleted or suspended by usertasks - True / False ?

14. The idle task consumes some of the processor resources - True / False ? How to reduce the resource usage ?

15. What are the various states of task in uC/OS-II RTOS ?

16. Explain Task Scheduling in uC/OS-II RTOS ?

17. Task-level scheduling and ISR-level scheduling are done by OS_Sched() and OSIntExit(), respectively - True/False ?

18. Task level scheduling invokes a software interrupt for context switches in uC/OS-II RTOS - True / False ?

19. Why are interrupts disabled while identifying the high-prirority ready task ?

20. Which API services Clock ticks ?

21. uC/OS-II RTOS lacks soft realtime support - True / False.

22. Does uC/OS-II RTOS support sempahore / Tell about OSSemPend and OSsemPost use ?

23. Tell about the use of mailbox in uC/OS=II RTOS ?

24. If there is already a message in the mailbox, then an error is returned, and also it is not overwritten - True/False

25. uC/OS-II does not automatically check for the status of stacks - True/False

26. What is the use of OSTaskStkCheck() ?

27. How will you port uC/OS-II RTOS ?

28. While porting, Where do you do the compiler specific data type and processor specific changes for porting uC/OS-II RTOS or What are the changes specific to OS_CPU.h ?

29. WHat is the use of HOOK functions / APIs ?

30. How can you identify the exten to which the CPU is busy ?

31. WHere do you do the interrupt related processor specific changes for porting uC/OS-II RTOS ? or What are the changes to be done in OS_CPU_A.ASM ?

32. Tell about Message Queues operation ?

33. What is the difference between Mailbox and Message queue in uC/OS-II RTOS ?

34. What are hooks ?